The present invention relates to phase shift circuits.
One simple method of providing a phase shifted signal is to include a delay element in a clock signal path. Disadvantages of this simple approach include the following: (1) it provides the desired phase shift for only a specific input clock frequency, (2) it has wide variation across process, voltage, and temperature (PVT), and (3) it requires testing/characterization in the production flow, i.e., during the manufacturing process, to determine if the phase shift is within an acceptable range.
A second method of generating a phase shifted signal is to use a phase-locked loop (PLL) circuit. In one PLL circuit, OSC, the output of the voltage controlled oscillator (VCO), is provided to a divide-by-2 circuit. The output of the divide-by-2 circuit, OSC1/2, which has a frequency that is half that of OSC, is then provided to the phase frequency detector (PFD). OSC is also sent to a negative edge-triggered divide-by-2 circuit. When the VCO is locked, the output of the negative edge-triggered divide-by-2 circuit is CLK90, which is CLKIN phase shifted by 90 degrees. Disadvantages of this method include (1) relatively low yield, (2) need for testing in production, (3) difficultly to migrate as semiconductor process scales are reduced, (4) susceptibility to power and ground noises, and (5) locking difficulties.
A third method of generating a phase shifted signal is to use a delay-locked loop (DLL) circuit. FIG. 1 is a block diagram illustrating a DLL circuit that provides phase shifted signals. In FIG. 1, DLL circuit 100 includes four delay chains 110, 120, 130, and 140 with four corresponding multiplexors 115, 125, 135, and 145. Each of the first through fourth delay chains is a ¼ N-tap delay chain, where T is the period of an input clock signal CLKIN 101 and N is an integer. Each delay chain includes N delay units, whose collective delay is ¼ T, where each delay unit produces a delay of T/(4N). Each delay chain provides its N delayed outputs to its respective multiplexor, where the delay of the first output is 0 and increases by T/(4N) for each consecutive output. Each of multiplexors 115, 125, 135, and 145 is an N by 1 multiplexor.
First delay chain 110 receives input clock signal CLKIN 101 and provides N delayed signals to first multiplexor 115. Output 116 (also referred to as CLK90) of first multiplexor 115 is input to second delay chain 120. Second delay chain 120 provides N delayed signals to second multiplexor 125. Output 126 (also referred to as CLK180) of second multiplexor 125 is input to third delay chain 130. Third delay chain 130 provides N delayed signals to third multiplexor 135. Output 136 (also referred to as CLK270) of third multiplexor 135 is input to fourth delay chain 140. Fourth delay chain 140 provides N delayed signals to fourth multiplexor 145. Output 146 (also referred to as CLK360) of fourth multiplexor 145 is sent to phase detector 160.
Phase detector 160 also receives CLKIN. Phase detector 160 provides information regarding the phase difference between CLKIN and CLK360 to control circuit 170. If CLKIN is not in phase with CLK360, then control circuit 170 will send control signal 171 to the first through fourth multiplexors to select the next delayed output from their respective delay chains such that all four multiplexors advance together. When CLKIN and CLK360 are in phase, control circuit 170 will send control signal 171 to the first through fourth multiplexors to maintain their current selections. Thus, the DLL is locked at the selected delays. When the DLL is locked, CLK 90, CLK180, CLK270, and CLK360 are respectively 90, 180, 270, and 360 degrees phase shifted with respect to CLKIN.
If as a result of input clock frequency change or PVT variation, CLK360 is no longer in phase with CLKIN, then control circuit 170 will signal the first through fourth multiplexors to select the next or previous delayed output from their respective delay chains such that all four multiplexors advance or retreat together. This process will continue until CLKIN and CLK360 are in phase again and the DLL is relocked.
DLL circuit 100 provides a number of advantages with respect to one or both of the two other options described above. First, it can be a 100% digital and therefore provides higher yield than a circuit that is less than 100% digital. It is simple to implement and, thus, can be implemented relatively quickly with relatively limited resources. Its simple implementation guarantees locking and relocking without testing in production because it includes a control circuit. It also has the advantages of ease of migration as semiconductor manufacturing processes advance, working with any power supply level, having less clock jitter, and being less susceptible to power noise level.
Despite the above advantages, the DLL circuit also has the following disadvantages. First, it requires a relatively large amount of area. Each of the four delay chains requires a large area. Similarly, each of the four multiplexors also requires a large area, especially since the paths for all the multiplexor inputs are matched. Second, the delay chains, if long, may require a significant amount of power. Third, the intrinsic delay of the first through fourth multiplexors limit the maximum frequency Fmax of the input clock signal CLKIN. The intrinsic delay increases with a lower CLKIN frequency as that requires a longer delay chain, which in turn requires a larger multiplexor. Thus, a lower CLKIN Fmin (minimum CLKIN frequency) specification results in a lower CLKIN Fmax. To compensate for the limitation on Fmax by the intrinsic delay, some DLL circuits offer only two phases (e.g., 0 and 180 degrees) in high frequency mode (i.e., when the frequency of CLKIN is high) rather than the four phases (e.g., 0, 90, 180, and 270 degrees) offered in low frequency mode (i.e., when the frequency of CLKIN is low). Reducing the number of phases offered allows for increasing Fmax because in that case some multiplexors are bypassed thus removing their intrinsic delay and reducing the overall intrinsic delay. However, this approach to compensate for limitations on Fmax does so at the expense of eliminating previously offered phase shifts. Moreover, it fails to address all the disadvantages mentioned above.